1. Field of the Invention
The present invention relates to bandgap reference voltage generator circuits, and in particular, to bandgap reference voltage generator circuits using current regeneration techniques.
2. Description of the Related Art
Bandgap reference voltage generator circuits come in a variety of configurations and can be implemented using either, or both, bipolar or metal oxide semiconductor (MOS) transistors. For example, such a circuit can be implemented in a bipolar and complementary MOS (BiCMOS) process and designed to require less than 100 nanoamperes of supply current from the power supply voltage VCC source.
Referring to FIG. 1, one conventional bipolar circuit uses two current mirror circuits Q1/Q2, Q3/Q4 cross-coupled in a telescopic circuit configuration. Hence, the input I1 and output I2 currents of the PNP current mirror circuit Q1/Q2 serve as the output and input currents, respectively, of the NPN current mirror circuit Q3/Q4. Transistor Q2 is typically scaled with a larger emitter area than transistor Q1 (e.g., 3:1), and transistor Q4 is typically scaled to have an emitter area larger than that of transistor Q3 (e.g., 10:1). The resulting bandgap voltage VBG is typically designed to be 1.2 volts.
Frequently, the most important operating characteristic for this type of circuit is its startup characteristic. For example, a fast rise time in the power supply voltage VCC will start it up. However, startup may not occur if the power supply voltage VCC is increased slowly and the temperature is very low (e.g., -55.degree. C.). This is due to the fact that the low current beta characteristic of the transistors Q1, Q2, Q3, Q4 is often too low to support sufficient leakage current to provide the current regeneration process necessary at very low temperatures, particularly over variations in the manufacturing processes. Further, even if the circuit initially starts up properly, in the event that the power supply voltage VCC drops low enough to shut down the circuit, the circuit may not turn back on once the supply voltage VCC has been returned to its correct value.
Referring to FIG. 2, a different situation is encountered when CMOS devices replace the bipolar devices. (This circuit is similar to that of FIG. 1 in that it is formed of a PMOS current mirror circuit M1/M2 cross-coupled with an NMOS current mirror circuit M3/M4 in a telescopic circuit configuration.) Transistors M2 and M4 are typically scaled to have wider channel dimensions than transistors M1 and M3, respectively (e.g., 3:1). Even at very low temperatures, the leakage current through a MOS transistor is not zero, notwithstanding the sophisticated processes presently used in fabricating the devices. Either the NMOS or PMOS devices are going to leak more than the other devices.
For example, in the event that the NMOS transistor leak more, the leakage current in transistor M4 will cause the PMOS transistors M1, M2 to turn on (due to the biasing of the gate-source region of transistor M1 caused by the leakage current through transistor M4). As the voltage drop across the gate-source region of transistor M1 increases, current I1 increases. As current I1 increases, current I2, which is a scaled-up replica of current I1, causes the voltage potential at the gate terminals of transistors M3 and M4 to increase. This process continues until a sufficiently large current I1 flows through a resistor R2 to cause the loop gain to become unity. (It will be understood that if, instead, the PMOS transistors Ml, M2 had higher leakage currents than the NMOS transistors M3, M4, this same current regeneration process would take place.)